1. Field of the Invention
The present invention relates to a display control device for controlling a display.
2. Description of the Related Art
A display such as an active-matrix liquid crystal display and the like is publicly known. A display control device is used for controlling image representation on the display. FIG. 1 is a block diagram schematically showing a configuration of a conventional display control device used in the liquid crystal display. FIG. 2 is a timing chart showing an operation of the display control device shown in FIG. 1. FIG. 3 is a circuit diagram showing a configuration of a typical D flip-flop. The conventional display control device will be described below with reference to FIGS. 1 to 3.
As shown in FIG. 1, the display control device is provided with a shift register 1, a data hold block 4, a DA converter (DAC) 5 and an amplifier circuit (AMP) 6. The data hold block 4 includes a data register 2 and a data latch 3.
The shift register 1 has n (n is a natural number) D flip-flops that are connected in series. A clock signal is input to each D flip-flop. When one start pulse is input to the shift register 1 from the outside, the pulse is shifted through the D flip-flops in series in synchronization with the clock signal. The serially shifted pulse is referred to as a “shift pulse” hereinafter. As shown in FIG. 1, n shift pulses SCLK1 to SCLK(n) respectively output from the n D flip-flops are supplied to the data register 2.
As shown in FIG. 2, the shift pulses SCLK1 to SCLK(n) are output in series. In this manner, the shift register 1 outputs the shift pulses SCLK1 to SCLK(n) in series to the data register 2 based on the start pulse and the clock signal.
The data hold block 4 receives gradation data and a strobe signal in addition to the shift pulses SCLK1 to SCLK(n) output from the shift register 1. The gradation data are digital data corresponding to an image displayed on a liquid crystal panel of the liquid crystal display. As shown in FIG. 2, n gradation data (0Ah, 0Bh . . . ) corresponding to source outputs S1 to Sn are input in series to the data hold block 4.
More specifically, the data register 2 of the data hold block 4 has n D flip-flops. The n gradation data and the shift pulses SCLK1 to SCLK(n) are input to the n D flip-flops, respectively.
Each D flip-flop has a configuration as shown in FIG. 3, and receives a corresponding shift pulse as a clock signal. As shown in FIG. 2, the D flip-flops respectively hold the gradation data in response to the falling edges of the respective shift pulses SCLK1 to SCLK(n). That is, the data register 2 takes in the respective gradation data in synchronization with the shift pulses SCLK1 to SCLK(n). It should be noted that each gradation data is a data of plural bits, and each D flip-flop has the same bus width as each gradation data (not shown).
The data latch 3 of the data hold block 4 has n D flip-flops. The n D flip-flops are connected to outputs of the n D flip-flops of the data register 2, respectively. The strobe signal is input to the n D flip-flops of the data latch 3. Each D flip-flop is configured to receive data in response to the rising edge of the strobe signal. The strobe signal rises after all the gradation data are held by the data register 2, as shown in FIG. 2. In response to that, the data latch 3 receives simultaneously the all gradation data held by the data register 2.
The DA converter 5 receives the all gradation data from the data latch 3. Then, based on a reference voltage, the DA converter 5 converts respective gradation data into corresponding gradation voltages. The DA converter 5 outputs to the amplifier circuit 6 the gradation voltages corresponding to the respective gradation data. The amplifier circuit 6 amplifies the gradation voltages to generate source outputs 7 (output voltages S1 to Sn). Then, the amplifier circuit 6 applies the output voltages S1 to Sn to respective data lines of the liquid crystal panel.
In recent years, there is an increasing demand for a larger number of gradations in the liquid crystal display. In a case where the number of gradations is increased from 6 bits to 9 bits, for example, each of the data register 2, the data latch 3 and the DA converter 5 shown in FIG. 1 increases 1.5 times in circuit size. This causes increase in production cost of the display control device.
Moreover, in a test of the data hold block 4, various gradation data are written into the data hold block 4, and then the source outputs 7 output from the amplifier circuit 6 are analyzed. Here, the source outputs 7 include a plurality of output voltages S1 to Sn as described above, and manufacturing variability or the like affects the output voltages S1 to Sn. Even if the same gradation data is written into all the D flip-flops of the data register 2, the analog output voltages S1 to Sn are not always equal to each other due to the manufacturing variability or the like. It is therefore necessary to consider the influence of the manufacturing variability on the output voltages S1 to Sn when analyzing the outputs from the amplifier circuit 6.
FIG. 4A schematically shows an example of the variability of the source outputs 7. Specifically, the output voltages corresponding to the m-th gradation, the (m+1)-th gradation and the (m+2)-th gradation are shown. Each output voltage corresponding to any gradation has a certain distribution due to the manufacturing variability, and a judgment level for judging each gradation (each output voltage) has a certain width. In FIG. 4A, there is no overlap between the judgment levels of adjacent gradations.
However, the difference between the judgment levels of the adjacent gradations is becoming smaller because of the increase in the number of gradations and decrease in an operation voltage. In FIG. 4B, the difference between the judgment levels of the adjacent gradations is smaller than the variability width of the output voltage, and thus there is an overlap between the judgment levels of the adjacent gradations. In this case, it is difficult to determine which of the adjacent gradations corresponds to an output voltage. In other words, it is difficult to test the data hold block 4 by checking the gradation data based on the output voltage. In particular, it is difficult to test the low-order bit of the gradation data.
FIG. 5 shows a waveform of one output voltage output from the amplifier circuit 6. As shown in FIG. 5, the width of the judgment level for judging the output voltage is small. From the aspect of electric power consumption, it is not desirable to enhance drive ability of the amplifier circuit 6. Therefore, a lot of time is necessary for testing the data hold block 4 based on the source output 7 output from the amplifier circuit 6.
Japanese Laid-Open Patent Application JP-P2004-301513 discloses a semiconductor device having a liquid crystal driving circuit and a method of testing the same. The liquid crystal driving circuit is provided with a digital function unit, an analog function unit and a test terminal. The digital function unit and the analog function unit are functionally separated from each other. A test result with respect to the digital function unit is transferred to the test terminal without through the analog function unit and is output to the outside of the liquid crystal driving circuit.